Commercially available RISC-V silicon

The RISC-V instruction set architecture has seen huge excitement and growth in recent years (10B cores estimated to have shipped as of Dec 2022) and I've been keeping very busy with RISC-V related work at Igalia. I thought it would be fun to look beyond the cores I've been working with and to enumerate the SoCs that are available for direct purchase or in development boards that feature RISC-V cores programmable by the end user. I'm certain to be missing some SoCs or have some mistakes or missing information - any corrections very gratefully received at asb@muxup.com or asbradbury.org on bsky. I'm focusing almost exclusively on the RISC-V aspects of each SoC - i.e. don't expect a detailed listing of other on-chip peripherals or accelerators.

A few thoughts

• It was absolutely astonishing how difficult it was to get basic information about the RISC-V specification implemented by many of these SoCs. In a number of cases, just a description of a "RV32 core at xxMHz" with further detective work being needed to find any information at all about even the standard instruction set extensions supported.
• The way I've focused on the details of individual cores does a bit of a disservice to those SoCs with compute clusters or interesting cache hierarchies. If I were to do this again (or if I revisit this in the future), I'd look to rectify that. There a whole bunch of other micro-architectural details it would be interesting to detail too.
  • I've picked up CoreMark numbers where available, but of course that's a very limited metric to compare cores. It's also not always clear which compiler was used, which extensions were targeted and so on. Plus when the figure is taken from an IP core product page, the numbers may refer to a newer version of the IP. Where there are multiple numbers floating about I've listed them all.
• There's a lot of chips here - but although I've likely missed some, not so many that it's impossible to enumerate. RISC-V is growing rapidly, so perhaps this will change in the next year or two.
• A large proportion of the SoC designs listed are based on proprietary core designs. The exceptions are the collection of SoCs based on the T-Head cores, the SiFive E31 and Kendryte K210 (Rocket-derived) and the GreenWaves GAP8/GAP9 (PULP-derived). As a long-term proponent of open source silicon I'd hope to see this change over time. Once a company has moved from a proprietary ISA to an open standard (RISC-V), there's a much easier transition path to switch from a proprietary IP core to one that's open source.

64-bit Linux-capable application processors

• StarFive JH7110
  • Core design:
    • 4 x RV64GC_Zba_Zbb SiFive U74 application cores, 1 x RV64IMAC SiFive S7 (this?) monitor core, and 1 x RV32IMFC SiFive E24 (ref, ref).
    • The U74 is a dual-issue in-order pipeline with 8 stages.
  • Key stats:
    • 1.5 GHz, fabbed on TSMC 28nm (ref).
    • StarFive report a CoreMark/MHz of 5.09.
  • Development board:
    • Available in the VisionFive 2 and Pine64 Star64 development boards.
• T-Head C910 ICE
  • Core design:
    • 2 x RV64GC T-Head C910 application cores and an additional T-Head C910 RV64GCV core (i.e., with the vector extension).
    • The C910 is a 3-issue out-of-order pipeline with 12 stages.
  • Key stats:
    • 1.2 GHz, fabbed on a 28nm process (ref).
  • Development board:
    • Available in the RVB-ICE.
• Allwinner D1-H (datasheet, user manual)
  • Core design:
    • 1 x RV64GC T-Head C906 application core. Additionally supports the unratified, v0.7.1 RISC-V vector specification (ref).
    • Single-issue in-order pipeline with 5 stages.
    • Verilog for the core is on GitHub under the Apache License (see discussion on what is included).
    • At least early versions of the chip incorrectly trapped on fence.tso. It's unclear if this has been fixed in later revisions.
  • Key stats:
    • 1GHz, taped out on a 22nm process node.
    • Reportedly 3.8 CoreMark/MHz.
  • Development board:
    • Available in a number of development boards (e.g. Allwinner Nezha, SiPeed Lichee RV, and more).
• StarFive JH7100
  • Core design:
    • 2 x RV64GC SiFive U74 application cores and 1 x RV32IMAFC SiFive E24.
    • The U74 is a dual-issue in-order pipeline with 8 stages.
  • Key stats:
    • 1.2GHz (as listed on StarFive's page but articles about the V1 board claimed 1.5GHz), presumably fabbed on TSMC 28nm (the JH7110 is).
    • The current U74 product page claims 5.75 CoreMark/MHz (previous reports suggested 4.9 CoreMark/MHz).
  • Development board:
    • Available on the VisionFive V1 development board.
• Kendryte K210 (datasheet)
  • Core design:
    • 2 x RV64GC application cores (reportedly implementations of the open-source Rocket core design).
    • If it's correct the K210 uses Rocket, it's a single-issue in-order pipeline with 5 stages.
    • Has a non-standard (older version of the privileged spec?) MMU (ref, so the nommu Linux port is typically used.
  • Key stats:
    • 400MHz, fabbed on TSMC 28nm.
  • Development board:
    • Available in development boards from SiPeed.
• MicroChip PolarFire SoC MPFSxxxT
  • Core design:
    • 4 x RV64GC SiFive U54 application cores, 1 x RV64IMAC SiFive E51 (now renamed to S51) monitor core.
    • The U54 is a single-issue, in-order pipeline with 5 stages.
  • Key stats:
    • 667 MHz (ref), fabbed on a 28nm node (ref).
    • Microchip report 3.125 CoreMark/MHz.
  • Development board:
    • Available in the 'Icicle' development board.
• SiFive FU740
  • Core design:
    • 4 x RV64GC SFive U74 application cores, 1 x RV64IMAC SiFive S71 monitor core.
    • It's hard to find details for the S71 core, the FU740 manual refers to it as an S7 while the HiFive Unmatched refers to it as the S71 - but neither have a page on SiFive's site. I'm told that the S71 has the same pipeline as the S76, just no support for the F and D extensions.
    • The U74 is a dual-issue in-order pipeline with 8 stages.
  • Key stats:
    • 1.2 GHz, fabbed on TSMC 28nm (ref).
    • The current U74 product page claims 5.75 CoreMark/MHz (previous reports suggested 4.9 CoreMark/MHz).
  • Development board:
    • Was available on the now-discontinued HiFive Unmatched development board.
• SiFive FU540
  • Core design:
    • 4 x RV64GC SiFive U54 application cores, 1 x RV64IMAC SiFive E51 (now renamed to S51) monitor core.
    • The U54 is a single-issue, in-order pipeline with 5 stages.
  • Key stats:
    • 1.5GHz, fabbed on TSMC 28nm (ref).
    • The current U54 product page claims 3.16 CoreMark/MHz but it was 2.75 in 2017.
  • Development board:
    • Was available on the now-discontinued HiFive Unleashed development board.
• Bouffalo Lab BL808
  • Core design:
    • 1 x RV64IMAFCV T-Head C906 application core, 1 x RV32IMAFCP T-Head E907, 1 x RV32E?? T-Head E902 (ref).
    • See notes elsewhere for more info on these T-Head core designs.
  • Key stats:
    • The C906 runs at 480 MHz, the E907 at 320 MHz and the E902 at 150 MHz.
  • Development board:
    • Available in the Ox64 from Pine64.
• Renesas RZ/Five
  • Core design:
    • 1 x RV64GC Andes AX45MP application core with additional Andes extensions (draft of the 'P' packed SIMD spec, Andes 'V5' extensions).
    • Unfortunately has a hardware bug where virtual addresses in a certain range are always treated as physical addresses.
    • Dual issue, in-order pipeline with 8 stages.
  • Key stats:
    • 1.0 GHz, 5.63 CoreMark/MHz (ref).
  • Development board:
    • Evaluation kit available.
• Kendryte K510
  • Core design:
    • 2 x RV64GC application cores and 1 x RV64GC core with DSP extensions. The Andes AX25MP appears to be used (ref).
  • Key stats:
    • 800 MHz.
  • Development board:
    • K510 CRB-KIT developer kit is available.
• (Upcoming) Intel-SiFive Horse Creek SoC
  • Core design:
    • 4 x "RV64GBC" SiFive P550 application cores (docs not yet available, but an overview is here). As the 'B' extension was broken up into smaller sub-extensions, this is perhaps RV64GC_Zba_Zbb like the SiFive U74.
    • 13 stage, 3 issue, out-of-order pipeline.
    • As the bit manipulation extension was split into a range of sub-extensions it's unclear exactly which of the 'B' family extensions will be supported.
  • Key stats:
    • 2.2 GHz, fabbed on Intel's '4' process node (ref).
  • Development board:
    • Will be available in the HiFive Pro P550 development board.
• (Upcoming) T-Head TH1520 (announcement)
  • Core design:
    • 4 x RV64GC T-Head C910 application cores, 1 x RV64GC T-Head C906, 1 x RV32IMC T-Head E902.
    • The C910 is a 3-issue out-of-order pipeline with 12 stages, the C906 is single-issue in-order with 5 stages, and the E902 is single-issue in-order with 2 stages.
    • Verilog for the cores is up on GitHub under the Apache license: C910, C906, E902. See discussion on what is included).
  • Key stats:
    • 2.4 GHz, fabbed on a 12nm process (ref).
  • Development board:
    • Will be available on the SiPeed Lichee Pi 4A.

Embedded / specialised SoCs (mostly 32-bit)

• SiFive FE310
  • Core design:
    • 1 x RV32IMAC SiFive E31 core.
    • Single-issue, in-order pipeline with 5 stages.
    • Derived from the open source Rocket core design (ref).
  • Key stats:
    • 320 MHz (ref), fabbed on TSMC 180nm (ref),
    • 2.73 CoreMark/MHz in the FE310-G002 datasheet, 3.17 CoreMark/MHz on the E31 product page.
  • Development board:
    • Available in development boards such as the HiFive 1 Rev B.
• GigaDevice GD32VF103 series
  • Core design:
    • 1 x RV32IMAC Nuclei Bumblebee N200 ("jointly developed by Nuclei System Technology and Andes Technology.")
    • No support for PMP (Physical Memory Protection), includes the 'ECLIC' interrupt controller derived from the CLIC design.
    • Single-issue, in-order pipeline with 2 stages.
  • Key stats:
    • 108 MHz. 360 CoreMark (ref), implying 3.33 CoreMark/MHz.
  • Development board:
    • Available in development boards such as the Sipeed Longan Nano.
• GreenWaves GAP8
  • Core design:
    • Fabric Controller (FC) core and compute cluster of 8 cores based on PULP. Implements RV32IMC with alongside additional custom extensions.
  • Key stats:
    • 175 MHz Fabric Controller, 250 MHz cluster. Fabbed on TSMC's 55nm process (ref).
    • 22.65 GOPS at 4.24mW/GOP (ref).
    • Shipped 150,000 units, composed of roughly 80% open source and 20% proprietary IP (ref).
  • Development board:
    • Available in the GAPuino.
• GreenWaves GAP9
  • Core design:
    • Fabric Controller (FC) and compute cluster of 9 cores. Extends the RV32IMC (plus extensions) GAP8 core design with additional custom extensions (ref).
  • Key stats:
    • 400 MHz Fabric Controller and computer cluster. Fabbed on Global Foundries 22nm FDX process (ref).
    • 150.8 GOPS at 0.33mW/GOP (ref).
  • Development board:
    • GAP9 evaluation kit listed on Greenwaves store but you must email to receive access to order it.
• Renesas RH850/U2B
  • Core design:
    • Features an NSITEXE DR1000C RISC-V parallel coprocessor, comprised of RV32I scalar processor units, a control core unit, and a vector processing unit based on the RISC-V vector extension.
  • Key stats:
    • 400 MHz. Fabbed on a 28nm process.
  • Development board:
    • None I can find.
• Renesas R9A02G020
  • Core design:
    • 1 x RV32IMC AndesCore N22 (additionally supporting the Andes 'Performance' and 'CoDense' instruction set extensions).
    • Single-issue in-order with a 2-stage pipeline.
  • Key stats:
    • 32 MHz.
  • Development board:
    • The R9A02G020-EVK motor control kit is available.
• Analog Devices MAX78000
  • Core design:
    • Features an RV32 RISC-V coprocessor of unknown (to me!) design and unknown ISA naming string.
  • Key stats:
    • 60 MHz (for the RISC-V co-processor), fabbed on a TSMC 40nm process (ref).
  • Development board:
    • MAX78000EVKIT and MAX78000FTHR.
• Espressif ESP32-C3 / ESP8685
  • Core design:
    • 1 x RV32IMC core of unknown design, single issue in-order 4-stage pipeline (ref).
  • Key stats:
    • 160 MHz, fabbed on a TSMC 40nm process (ref).
    • 2.55 CoreMark/MHz.
  • Development board:
    • Available in a number of formats including the ESP32-C3-DevKitM-1 and the M5Stack M5Stamp C3.
• Espressif ESP32-C2 / ESP8684
  • Core design:
    • 1 x RV32IMC core of unknown design, single issue in-order 4-stage pipeline (ref).
  • Key stats:
    • 160 MHz, fabbed on a TSMC 40nm process.
    • 2.55 CoreMark/MHz.
    • Die photo available in this article.
  • Development board:
    • Available in the ESP8684-DevKitM-1-H4.
• Espressif ESP32-C6
  • Core design:
    • 1 x RV32IMAC core of unknown design (four stage pipeline) and 1 x RV32IMAC core of unknown design (two stage pipeline) for low power operation (ref).
  • Key stats:
    • 160 MHz high performance (HP) core with 2.76 CoreMark/MHz, 20 MHz low power (LP) core.
  • Development board:
    • Available in the ESP32-C6-DevKitC-1-N8.
• HiSilicon Hi3861
  • Core design:
    • 1 x RV32IM core of unknown design, supporting additional non-standard compressed instruction set extensions (ref).
  • Key stats:
    • 160 MHz.
  • Development board:
    • A low-cost board is available advertising support for Harmony OS.
• Bouffalo Lab BL616/BL618
  • Core design:
    • 1 x RV32GC core of unknown design, also with support for the unratified 'P' packed SIMD extension (ref).
  • Key stats:
    • 320 MHz.
  • Development board:
    • Available in the Sipeed M0S module.
• Bouffalo Lab BL602/BL604
  • Core design:
    • 1 x RV32IMAFC SiFive E24 core (ref).
    • 3-stage pipeline.
  • Key stats:
    • 192 MHz, 3.1 CoreMark/MHz (ref).
  • Development board:
    • Available in the very low cost Pinecone evaluation board.
  • Other:
    • The BL702 appears to have the same core, so I haven't listed it separately.
• Bluetrum AB5301A
  • Core design:
    • 1 x RV32 core of uknown design and unknown ISA naming string (CNX Software tried and failed to get clarification.
  • Key stats:
    • 125 MHz.
  • Development board:
    • Available in the AB32VG1 development board.
• WCH CH583/CH582/CH581
  • Core design:
    • 1 x RV32IMAC QingKe V4a core, which also supports a "hardware prologue/epilogue" extension.
    • Single issue in-order pipeline with 2 stages.
    • Unlike the other QingKe V4 series core designs, the V4a doesn't support the custom 'extended instruction' (XW) instruction set extension.
  • Key stats:
    • 20MHz.
  • Development board:
    • An evaluation board is available.
• WCH CH32V307
  • Core design:
    • 1 x RV32IMAFC QingKe V4f core.
  • Key stats:
    • 144 MHz.
  • Development board:
    • An evaluation board is available.
• WVH CH32V208
  • Core design:
    • 1 x RV32IMAC QingKe V4c core with custom instruction set extensions ('XW' for sign-extended byte and half word operations).
  • Key info:
    • 144 MHz.
  • Development board:
    • Available here.
  • Other:
    • The CH32V203 is also available but I haven't listed it separately as it's not clear how the QingKe V4b core in that chip differs to the V4c in this one.
• WCH CH569 / WCH CH573 / WCH CH32V103
  • Core design:
    • 1 x RV32IMAC QinqKe V3a core.
  • Key stats:
    • 120 MHz (CH569), 20 MHz (CH573), 80 MHz (CH32V103).
  • Development board:
    • Evaluation boards available, e.g. this one for the CH32V103.
• WCH CH32V003
  • Core design:
    • 1 x RV32EC QingKe V2A with custom instruction set extensions ('XW' for sign-extended byte and half word operations).
  • Key stats:
    • 48 MHz.
    • Notably announced as costing less than 10 cents.
  • Development board:
    • Various boards available.
• PicoCom PC802
  • Core design:
    • Two clusters of 16 RV32IMAC Andes N25F cores (ref).
    • Single issue, in order pipeline with 5 stages.
    • Also see the 2021 RISC-V summit talk for more insight on the architecture.
  • Key stats:
    • Fabbed on TSMC 12nm process (ref).
  • Development board:
    • Several boards are available.
• CSM32RV20
  • Core design:
    • 1 x RV32IMAC core of unknown design.
  • Key stats:
    • 2.6 CoreMark/MHz.
  • Development board:
    • The product page suggests two boards are available.
• HPMicro HPM6750
  • Core design:
    • 2 x RV32IMAFDC cores (AndesCore D45) with an implementation of the draft 'P' packed SIMD spec (ref).
    • In-order dual-issue 8-stage pipeline.
  • Key stats:
    • 800 MHz
  • Development board:
    • Available in the HPM6750EVK as well as other variants.
• Renesas R9A06G150
  • Core design:
    • 1 x RV32IMAFC AndesCore D25F with additional vendor-specific instruction set extensions.
    • 5 stage pipeline, single issue in-order.
  • Key stats:
    • 100 MHz
  • Development board:
    • None available currently.

Bonus: Other SoCs that don't match the above criteria or where there's insufficient info

• The Espressif ESP32-P4 was announced, featuring a dual-core 400MHz RISC-V CPU with "an AI instructions extension". I look forward to incorporating it into the list above when more information is available.
• I won't try to enumerate every use of RISC-V in chips that aren't programmable by end users or where development boards aren't available, but it's worth noting the use of RISC-V Google's Titan M2
• In January 2022 Intel Mobileye announced the EyeQ Ultra featuring 12 RISC-V cores (of unknown design), but there hasn't been any news since.